文章基本信息

标题：Design of Low Power Consumption and Area Efficient Modified Carry Select Adder with D-Latch on a Reconfigurable Hardware
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作者：C. Dharsana ; G.Dhivya ; D.Dhivya 等
期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2017
卷号：5
期号：3
页码：4907
DOI：10.15680/IJIRCCE.2017.0503232
出版社：S&S Publications
摘要：Design of area- and power-efficient high-speed data path logic systems are one of the most substantialareas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required topropagate a carry through the adder. Carry SeLect Adder (CSLA) is one of the fastest adders used in many dataprocessingprocessors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there isscope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-levelmodification to significantly reduce the area and power of the CSLA. Based on this modification 8-bit, 16-bit, 32-bit,and 64-bit square-root CSLA architecture have been developed and compared with the regular SQRT CSLAarchitecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only aslight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area,power.
关键词：Application-specific integrated circuit (ASIC); area-efficient; CSLA; low power; SQRT CSLA