文章基本信息

标题：Design of 16 bit multiplier for Posit data format
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作者：Narayana M Hegde ; Kiran V
期刊名称：International Journal of Advances in Engineering and Management
电子版ISSN：2395-5252
出版年度：2021
卷号：3
期号：9
页码：104-107
DOI：10.35629/5252-030818291839
语种：English
出版社：IJAEM JOURNAL
摘要：Multiplication is one of the most commonly used operations of all the arithmetic operations in various applications. In this paper, a multiplier architecture for the posit number system is proposed. Posit number system provides better dynamic range and accuracy compared to floatingpoint numbers (IEEE 754 standard) for the same word size. The dynamic range and precision of posits can be attributed to an exponent component with run-time varying length. Due to these run-time variations, hardware design is challenging. So, in this paper multiplier for posits is constructed in Verilog HDL.
关键词：Unum;Posit;Multiplier